Question: Repeat the analysis of Problem 23 with

> Show the connection (including pin information) of two LM358 stages connected as unity-gain amplifiers to provide the same output.

> Calculate the output voltage for the circuit of Fig. 11.47 for an input of Vi = 3.5 mV rms.

> Calculate the output voltage of the circuit in Fig. 10.68 for Rf = 68 kΩ.

> Calculate the output voltage developed by the circuit of Fig. 10.68 for Rf = 330 kΩ.

> What range of output voltage is developed in the circuit of Fig. 10.67?

> What input must be applied to the input of Fig. 10.66 to result in an output of 2.4 V?

> What output voltage results in the circuit of Fig. 10.66 for an input of V1 = —0.3 V?

> What is the range of the output voltage in the circuit of Fig. 10.65 if the input can vary from 0.1 to 0.5 V?

> What input voltage results in an output of 2 V in the circuit of Fig. 10.64?

> a. Using the characteristics of Fig. 4.121, determine RC and RE for a voltage-divider network having a Q-point of ICQ = 5 mA and VCEQ = 8 V. Use VCC = 24 V and RC = 3RE. b. Find VE. c. Determine VB. d. Find R2 if R1 = 24 kΩ assuming that RE  10R2. e. C

> Determine the output voltage of an op-amp for input voltages of Vi1 = 200 mV and Vi2 = 140 mV. The amplifier has a differential gain of Ad = 6000 and the value of CMRR is: a. 200. b. 105.

> Calculate the CMRR (in dB) for the circuit measurements of VD = 1 mV, VO = 120 mV, VC = 1 mV, and VO = 20 mV.

> For the typical characteristics of the 741 op-amp, calculate the following values for the circuit of Fig. 10.75: a. ACL. b. Zi. c. Zo.

> Using the specifications listed in Table 10.3; calculate the typical offset voltage for the circuit connection of Fig. 10.75.

> For an input of V1 = 50 mV in the circuit of Fig. 10.75, determine the maximum frequency that may be used. The op-amp slew rate SR = 0.4 V>ms.

> What is the range of the voltage-gain adjustment in the circuit of Fig. 10.63?

> For an op-amp having a slew rate of SR = 2.4 V>ms, what is the maximum closed-loop volt- age gain that can be used when the input signal varies by 0.3 V in 10 ms?

> Determine the cutoff frequency of an op-amp having specified values B1 = 800 kHz and AVD = 150 V>mV.

> Calculate the input bias current at each input of an op-amp having specified values of IIO = 4 nA and IIB = 20 nA.

> Calculate the total offset voltage for the circuit of Fig. 10.75 for an op-amp with specified values of input offset voltage VIO = 6 mV and input offset current IIO = 120 nA.

> a. Determine ICQ, VCEQ, and IBQ for the network of Problem 15 (Fig. 4.125) using the approxi- mate approach even though the condition established by Eq. (4.33) is not satisfied. b. Determine ICQ, VCEQ, and IBQ using the exact approach. c. Compare solutio

> Calculate VO in the circuit of Fig. 10.74.

> Calculate the output voltage, VO, in the circuit of Fig. 10.73.

> Calculate the output voltages V2 and V3 in the circuit of Fig. 10.72.

> Calculate the output voltage for the circuit of Fig. 10.71.

> What output voltage results in the circuit of Fig. 10.70 for V1 = +0.5 V?

> Sketch the output waveform resulting in Fig. 10.69.

> What is the output voltage in the circuit of Fig. 10.62?

> If the applied ac power to a system is 5 mW at 100 mV and the output power is 48 W, determine: a. The power gain in decibels. b. The voltage gain in decibels if the output impedance is 40 kΩ. c. The input impedance. d. The output voltage.

> a. The total decibel gain of a three-stage system is 120 dB. Determine the decibel gain of each stage if the second stage has twice the decibel gain of the first and the third has 2.7 times the decibel gain of the first. b. Determine the voltage gain of

> Input and output voltage measurements of VI = 10 mV and VO = 25 V are made. What is the voltage gain in decibels?

> Repeat Problem 21 using the exact (Thévenin) approach and compare solutions. Based on the results, is the approximate approach a valid analysis technique if Eq. (4.33) is satisfied?

> Two voltage measurements made across the same resistance are V1 = 110 V and V2 = 220 V. Calculate the power gain in decibels of the second reading over the first reading.

> Determine GdBm for an output power level of 25 W.

> Calculate the power gain in decibels for each of the following cases. a. Po = 100 W, Pi = 5 W. b. Po = 100 mW, Pi = 5 mW. c. Po = 100 mW, Pi = 20 mW.

> The application of a 10-mV, 100-kHz square wave to an amplifier resulted in the output wave- form of Fig. 9.90. a. Write the Fourier series expansion for the square wave through the ninth harmonic. b. Determine the bandwidth of the amplifier to the accur

> A four-stage amplifier has a lower 3-dB frequency for an individual stage of f1 = 40 Hz. What is the value of f1 for this full amplifier?

> Calculate the overall upper 3-dB frequency for a four-stage amplifier having an individual stage value of f2 = 2.5 MHz.

> Calculate the overall voltage gain of four identical stages of an amplifier, each having a gain of 20.

> Repeat the analysis of Problem 31 for the network of Fig. 9.89.

> For the network of Fig. 9.88: a. Determine gm0 and gm. b. Find Av and Avs in the mid-frequency range. c. Determine fHi and fHo. d. Sketch the frequency response for the high-frequency region using a Bode plot and determine the cutoff frequency. e. What i

> Repeat the analysis of Problem 27 for the network of Fig. 9.83 with Rs and Vs of Fig. 9.87.

> Determine the following for the voltage-divider configuration of Fig. 4.128 using the approxi- mate approach if the condition established by Eq. (4.33) is satisfied. a. IC. b. VCE. c. IB. d. VE. e. VB.

> Determine: a. 20 log10 (84) using Eq. (9.6) and compare with 20 log10 14. b. 10 log10 (1) using Eq. (9.7) and compare with 10 log10 4 * 10-3. c. log10 (40) (0.2) using Eq. (9.8) and compare with log10 8.

> Repeat the analysis of Problem 27 for the network of Fig. 9.82 with Rs and Vs of Fig. 9.86.

> Repeat the analysis of Problem 27 for the network of Fig. 9.81 with Rs and Vs of Fig. 9.85.

> For the network of Fig. 9.80 with Rs and Vs of Fig. 9.84: a. Determine fHi and fHo. b. Find fb and fT. c. Sketch the frequency response for the high-frequency region using a Bode plot and deter- mine the cutoff frequency. d. What is the gain-bandwidth pr

> a. The feedback capacitance of an inverting amplifier is 10 pF. What is the Miller capacitance at the input if the gain of the amplifier is —120? b. What is the Miller capacitance at the output of the amplifier? c. Is it a good approximation to assume CM

> Repeat the analysis of Problem 23 for the network of Fig. 9.89. What effect does the voltage- divider configuration have on the input impedance and the gain Avs compared to the biasing arrangement of Fig. 9.88?

> For the network of Fig. 9.88: a. Determine VGSQ and IDQ. b. Find gm0 and gm. c. Calculate the midband gain of Av = VO>VI. d. Determine Zi. e. Calculate Avs = VO>Vs. f. Determine fLG, fLC, and fLS. g. Determine the low-cutoff frequency. h. Sketch th

> a. Determine the common logarithm of the number 0.24 × 106. b. Determine the natural logarithm of the number of part (a) using Eq. (9.4). c. Determine the natural logarithm of the number of part (a) using natural logarithms and compare with the solution

> For the network of Fig. 9.80: a. Determine re. b. Find Avmid = VO>VI. c. Calculate Zi. d. Determine fLS, fLC, and fLE. e. Determine the low cutoff frequency. f. Sketch the asymptotes of the Bode plot defined by the cutoff frequencies of part (d). g. S

> a. Repeat problem 16 with  = 140 using the approximate approach and compare results. b. Is the approximate approach valid?

> Using the characteristics of Fig. 6.11, determine ID for the following levels of VGS (with VDS 7 VP): a. VGS = 0 V. b. VGS = —1 V. c. VGS = —1.5 V. d. VGS = —1.8 V. e. VGS = —4 V. f. VGS = —6 V.

> Repeat the analysis of Example 9.11 with ro = 40 kΩ. What is the effect on Avmid, fLS, fLC, fLE, and the resulting cutoff frequency?

> a. What frequency is one octave above 5 kHz? b. What frequency is one decade below 10 kHz? c. What frequency is two octaves below 20 kHz? d. What frequency is two decades above 1 kHz?

> For the network of Fig. 9.79: a. Determine the mathematical expression for the angle by which VO leads VI. b. Determine the phase angle at f = 100 Hz, 1 kHz, 2 kHz, 5 kHz, and 10 kHz, and plot the resulting curve for the frequency range of 100 Hz to 10 k

> For the network of Fig. 9.79: a. Determine the mathematical expression for the magnitude of the ratio VO>VI. b. Using the results of part (a), determine Vo>Vi at 100 Hz, 1 kHz, 2 kHz, 5 kHz, and 10 kHz, and plot the resulting curve for the frequenc

> Given the characteristics of Fig. 9.78, sketch: a. The normalized gain. b. The normalized dB gain (and determine the bandwidth and cutoff frequencies). /

> a. Determine the common logarithm of the following numbers: 103, 50, and 0.707. b. Determine the natural logarithm of the numbers appearing in part (a). c. Compare the solutions of parts (a) and (b).

> For a JFET having specified values of gfs = 4.5 mS and gos = 25 mS, determine the device output impedance Zo (FET) and device ideal voltage gain Av(FET).

> A specification sheet provides the following data (at a listed drain-source current): / At the listed drain–source current, determine: a. gm. b. rd.

> Determine the value of gm for a JFET (IDSS = 8 mA, VP = - 5 V) when biased at VGSQ = VP>4.

> A JFET (IDSS = 10 mA, VP = - 5 V) is biased at ID = IDSS>4. What is the value of gm at that bias point?

> Determine the saturation current (ICsat) for the network of Fig. 4.125.

> Calculate the input impedance (Zi) and output impedance (Zo) for the amplifier circuit of Fig. 8.94.

> For the amplifier circuit of Fig. 8.94, calculate the voltage gain of each stage and the overall amplifier voltage gain.

> For the cascade amplifier of Fig. 8.94, calculate the dc bias voltages currents of each stage.

> For the cascade amplifier of Fig. 8.93, using JFETs with specifications IDSS = 12 mA, VP = - 3 V, and gos = 25 mS, calculate the circuit input impedance (Zi) and output impedance (Zo).

> If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having the specifications IDSS = 12 mA, VP = - 3 V, and gos = 25 mS, calculate the resulting voltage gain for each stage, the overall voltage gain, and the output voltage, Vo.

> If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having specifications IDSS = 12 mA and VP = - 3 V, calculate the resulting dc bias of each stage.

> For the JFET cascade amplifier of Fig. 8.93, using identical JFETs with IDSS = 8 mA and VP = - 4.5 V, calculate the voltage gain of each stage, the overall gain of the amplifier, and the output voltage Vo.

> For the JFET cascade amplifier in Fig. 8.93, calculate the dc bias conditions for the two identical stages, using JFETs with IDSS = 8 mA and VP = - 4.5 V.

> For a JFET having gm = 6 mS at VGSQ = - 1 V, what is the value of IDSS if VP = - 2.5 V?

> Design the self-bias network of Fig. 8.89 to have a gain of 10. The device should be biased at VGSQ= 1VP.

> Given the information appearing in Fig. 4.127, determine: a. IC. b. VE. c. VCC. d. VCE. e. VB. f. R1.

> Design the fixed-bias network of Fig. 8.88 to have a gain of 8.

> Determine the output voltage for the network of Fig. 8.87 if VI = 0.8 mV and rd = 40 kΩ.

> Determine Vo for the network of Fig. 8.86 if Vi = 4 mV, V GS (Th) = 4 V, and ID (on) = 4 mA, with VGS (on) = 7 V and gos = 20 mS.

> Determine VO for the network of Fig. 8.86 if VI = 20 mV.

> Repeat Problem 41 if k drops to 0.2 * 10-3. Compare results.

> Determine Zi, Zo, and Av for the amplifier of Fig. 8.85 if k = 0.3 * 10-3.

> Determine gm for a MOSFET if VGS (Th) = 3 V and it is biased at VGSQ = 8 V. Assume k = 0.3 * 10-3.

> Calculate the value of gm for a JFET (IDSS = 12 mA, VP = - 3 V) at a bias point of VGS = - 0.5 V.

> Determine Zi, Zo, and Av for the network of Fig. 8.84.

> Determine Vo for the network of Fig. 8.83 if Vi = 1.8 mV.

> Given the information provided in Fig. 4.126, determine: a. IC. b. VE. c. VB. d. R1.

> Repeat Problem 36 if rd = 25 kΩ and compare results.

> Determine Zi, Zo, and Av for the network of Fig. 8.82 if rd = 60 kΩ.

> Determine Vo for the network of Fig. 8.81 if gos = 20 mS.

> Determine Zi, Zo, and Av for the network of Fig. 8.80.

> Repeat Problem 32 if rd = 20 kΩ and compare results.

> Determine Zi, Zo, and Av for the network of Fig. 8.79.

> Determine Zi, Zo, and Av for the network of Fig. 8.78 if rd = 30 kΩ.

> Repeat Problem 29 if rd = 20 kΩ and compare results.

> For a JFET having device parameters gm0 = 5 mS and VP = - 4 V, what is the device current at VGS = 0 V?

> Determine Zi, Zo, and Vo for the network of Fig. 8.77 if Vi = 4 mV

> a. Repeat problem 15 for  = 140 using the general approach (not the approximate). b. What levels are affected the most? Why?

> Repeat Problem 26 if rd = 20 kΩ and compare results.

> Repeat Problem 25 if rd = 20 kΩ and compare results.